Integrated circuits are designed by a highly complex design process. Typically, each stage of the design process provides more information about the designed integrated circuit, but is more costly and typically more complex. In addition, problems that are detected during later stages of the design process are typically harder to resolve, especially if their amendment requires performing earlier design process stages.
An integrate circuit includes multiple blocks and each block includes multiple internal components, input ports and output ports. An internal component can include a logic gate, (also referred to as a combinatory cell), a flip-flop, a transistor, or even a function. A block can be a core, a logic circuit, a memory unit, and the like. A block is typically re-used in different integrated circuits.
A typical design process of an integrated circuit block includes various stages. The design process can include receiving a register transfer level description and synthesizing the register transfer level description. This description can be transformed to a gate level design by synthesis. It is noted that the synthesis process can include a so-called placed and route stage that provides the layout of the block. This stage is followed by verifying the block design. Various vendors such as Cadence and Synopsis provide various tools such as that streamline the design process. Verilog and VHDL are known hardware description languages for describing blocks during the design process.
A known prior art tool for power estimation (such as Power Meter or Primepower) provides a power estimate after a gate level design of the block is generated. The power estimate is very accurate but is executed at a relatively late stage of the design process and requires a gate level run on a test pattern, which consumes time and machine time. Altering the design of the block at such a late stage of the design process is very costly and time consuming.